VHDL code for Decoder using Behavioral style of modeling

What is Decoder?

Decoder does the reverse operation of the encoder. By decoding we can obtain the original information from the encoded signal.

Circuit schematic of the Decoder:

(courtesy : Wikipedia )

Program:

--Library Declaration--
library ieee;
use ieee.std_logic_1164.all;
--Entity named DecoderBeh Declaration
entity DecoderBeh is
port(
--i port is for input--
i:in std_logic_vector(1 downto 0);
--e stands for enable--
e:in std_logic;
--y is for decoded output--
y:out std_logic_vector(3 downto 0));
end DecoderBeh;
--Architecture of Decoder--
architecture Dataflow of decoderbeh is
begin
process(i,e)
--Signal Declaration--
variable x:std_logic_vector(3 downto 0):="0000";
begin
--check for the input and depending on input
-- assign value to output
if(i="00" and e='1')
then
x:="1000";
elsif(i="01" and e='1')
then
x:="0100";
elsif(i="10" and e='1')
then
x:="0010";
elsif(i="11" and e='1')
then
x:="0001";
else x:="ZZZZ";
end if;
--Finally assign the signal value to output
y<=x;
end process;
end dataflow;

Output:

If you have any doubt on the above program or if you need further assistance please comment below ! :)