VHDL code for 3 bit comparator using full subtractor

Logic Design & Truth Table For Full Subtractor:

Simulation of Full-Subtracor: 



code for comparator--

library ieee;
use ieee.std_logic_1164.all;
entity comp_3bit is
port(a:in std_logic_vector(2 downto 0);
b:in std_logic_vector(2 downto 0);
agb,aeb,alb:inout std_logic);
end comp_3bit;
architecture dataflow of comp_3bit is
component fullsub is
port(a,b,c:in std_logic;
s,cout:out std_logic);
end component;
signal s,c:std_logic_vector(2 downto 0);
begin
a1:fullsub port map(a(0),b(0),'0',s(0),c(0));
a2:fullsub port map(a(1),b(1),c(0),s(1),c(1));
a3:fullsub port map(a(2),b(2),c(1),s(2),c(2));
agb<=aeb nor alb;
aeb<=not (s(0) or s(1) or s(2));
alb<=c(2);
end dataflow;

code for subtractor-- 


library ieee;
use ieee.std_logic_1164.all;
entity fullsub is
port(a,b,c:in std_logic;
s,cout:out std_logic);
end fullsub;
architecture dataflow of fullsub is
begin
s<=a xor b xor c;
cout<=(not a and (b or c)) or (b and c);
end dataflow;