code for 16:1 mux using FOR GENERATE

What is Mux ?

Mux is a digital device, which can have any number of inputs but only one output depending on the select lines.

Block schematics of 16:1 Mux 

Courtesy :Wikipedia 

Brief Description About Program :

In the following program 16:1 mux is realized using five 4:1 mux. Usually 'FOR GENERATE' used to generate the components repeatedly. 


VHDL CODE FOR 16:1 Mux


--------------------------------------------------------------------
-- Company : www.ProgrammedGeek.com 
-- Create Date : 12:58:00 01/10/2015 
-- Module Name : 16:1 Mux using 4:1 Mux 
--------------------------------------------------------------------

--Library declarations

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux_16 is
port
(
Data_In :in std_logic_vector(15 downto 0);
Select_In :in std_logic_vector(3 downto 0);
Data_Out :out std_logic
);
end Mux_16;

architecture Behavioral of Mux_16 is

--4:1 Mux Component Instantiation
component Mux_4 is
port
(
Data_In :in std_logic_vector(3 downto 0);
Select_In :in std_logic_vector(1 downto 0);
Data_Out :out std_logic
);
end component;

signal S_Data_Out:std_logic_vector(3 downto 0);
begin

--Stage 1 Mapping

G_MUX_4:for V_I in 0 to 3 generate
U_Mux_4_1:Mux_4
port map
(
Data_In => Data_In(V_I*4+3 downto V_I*4),
Select_In => Select_In(1 Downto 0),
Data_Out => S_Data_Out(V_I)
);
end generate;

--Stage 2 Mapping

U_Mux_4_2:Mux_4
port map
(
Data_In =>  S_Data_Out,
Select_In =>  Select_In(3 Downto 2),
Data_Out =>  Data_Out
);

end Behavioral;

code for 4:1 mux:

--------------------------------------------------------------------
-- Company : www.ProgrammedGeek.com 
-- Create Date : 15:07:22 01/10/2015 
-- Module Name : 4:1 Mux 
--------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux_4 is
port
(
Data_In :in std_logic_vector(3 downto 0);
Select_In :in std_logic_vector(1 downto 0);
Data_Out :out std_logic
);
end Mux_4;

architecture Behavioral of Mux_4 is

begin

--------------------------------------------------------------------
--Data Out is implemented using basic principle of the Mux as Shown 
-- Select line  | Data_Out
-- 00 | Data_In(3)
-- 01 | Data_In(2)
-- 10 | Data_In(1)
-- 11 | Data_In(0)
--------------------------------------------------------------------

Data_Out <= (not Select_In(1) and not Select_In(0) and Data_In(3) ) 
or (not Select_In(1) and Select_In(0) and Data_In(2)) 
or (Select_In(1) and not Select_In(0) and Data_In(1)) 
or (Select_In(1) and Select_In(0) and Data_In(0));

end Behavioral;

Schematic View :

Top level Block

16:1 Mux

4:1 Mux internal diagram

 Output :