VHDL CODE FOR D-FLIP FLOP WITH ASYNCHRONOUS RESET

WHAT IS D-FLIP FLOP?
The D flip-flop tracks the input, making transitions with match those of the input D. The D stands for "data". This flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying the set to the reset through an inverter. The result may be clocked.

Circuit diagram:

VHDL CODE:

---------------------------------------------
--LIBRARY DECLARATIONS--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---------------------------------------------
--ENTITY DECLARATION--
entity Dff_async_reset is
port(d,clk,rst:in std_logic;
 q:out std_logic
);
end Dff_async_reset;
----------------------------------------------
architecture Behavioral of Dff_async_reset is
begin

process(rst,clk)
begin
--SEQUENTIAL DECLARATION--
if(rst='1') then
--IF RESET IS 1 THEN SET OUTPUT TO 0
q<='0';
elsif(clk'event and clk='1') then
--IF THERE IS CHANGE IN CLK AND CLK IS HIGH
--SET OUTPUT AS INPUT
q<=d;
end if;
end process;

end Behavioral;
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OUTPUT: