VHDL CODE FOR MEMORY

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity memory is
port(
reset : in std_logic;
clk : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_out1 : out std_logic_vector(3 downto 0) ;
data_out2 : out std_logic_vector(3 downto 0)
);
end memory;

architecture Behavioral of memory is
begin
process(reset,clk,addr)

type temp_mem is array(0 to 3) of std_logic_vector(3 downto 0);
variable a : temp_mem := ( "0001", "0010", "0100", "1000" );
variable b : temp_mem := ( "1100", "0110", "0011", "1001" );

begin
if(reset = '0') then
data_out1 <= "0000";
data_out2 <= "0000";

elsif(clk='1' and clk'event) then
data_out1 <= a(CONV_INTEGER(addr(1 downto 0)));
data_out2 <= b(CONV_INTEGER(addr(1 downto 0)));
end if;
end process;
end Behavioral;