VHDL CODE FOR ALU USING BEHAVIORAL STYLE

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-- Company: 
-- Engineer:
--
-- Create Date:    12:53:29 05/22/08
-- Design Name:    
-- Module Name:    alu - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(7 downto 0);
e : in std_logic);
end alu;

architecture Behavioral of alu is
signal a1,b1:std_logic_vector(7 downto 0);
begin

process(e,a,b,s)
begin
a1<="0000"&a;
b1<="0000"&b;
if e='0' then
case s is
when"00"=>y<=a1+b1;
when"01"=>y<=a*b;
when"10"=>y<=a1 or b1;
when"11"=>y<=a1 xor b1;
when others=>null;
end case;
else y<="XXXXXXXX";
end if;
end process;



end Behavioral;