VERILOG CODE FOR T FLIP FLOP

PROGRAM:

module mytff(t,q,qb,clk);
input   t,clk;
output q,qb;
reg q,qb;
initial q=0;

always@(posedge clk)
begin
        if (t==1)
        begin
                q=~q;
              end
      else
        begin
      q=q;                
        end
        qb=~q;      
    end
endmodule

TEST BENCH :

`timescale 1ns/1ns

module tff (t,clk,q,qb);

input t,clk;

output q,qb;

reg q, qb;

initial

begin

q=0;

q=1;

end

always@(posedge (clk))

begin

if(t==0)

q=q;

else

q=qb;

qb=~q;

end

endmodule

`timescale 1ns/1ns

module tff_tb;

reg a,b;

wire y,yb;

tff out(.t(a), .clk(b),.q(y),.qb(yb));

initial

begin

a=0;

b=0;

#100;

b=1;

#100;

a=1;

b=0;

#100;

b=1;

#100;

end 

endmodule