VERILOG CODE FOR J-K FLIP FLOP

PROGRAM:

module myjkff(jk,clk,q,qb);

output q,qb;

input[1:0] jk;

input clk;

reg q,qb;

always @(posedge clk)

begin

      

                case(jk)

                        2'd1:q=0;

                        2'd2:q=1;

                        2'd3:q=~q;

                        2'd0:q=q;

                  endcase

          

         

          qb=~q;

     end

   endmodule

TEST BENCH :

`timescale 1ns/1ns

module jkff(j,k,clk,q,qb);

input j,k, clk;

output q, qb;

reg q,qb;

initial

begin

q=0;

qb=1;

end

always@ (posedge (clk))

begin

if(j==0 && k==0)

     q=0;

else if(j==0 && j==1)

     q=0;

else if (j==1 && k==0)

     q=1;

else q=qb;

     qb=~q;

end 

endmodule

`timescale 1ns/1ns

module jkff_tb;

reg a,b,c;

wire y,yb;

jkff out (.j(a), .k(c),.clk(b), .q(y), .qb(yb));

initial

begin

c=0;

a=0;

b=0;

#100;

b=1;

#100;

a=1;

b=0;

#100;

b=1;

#100;

c=1;

a=0;

b=0;

#100;

a=0;

b=1;

#100;

a=1;

#100;

b=1;

#100;

end

endmodule