1. How are blocking and non-blocking statements executed?
Answer
In a blocking statement, the RHS will be evaluated and the LHS will be then updated, without interruption from any other Verilog statement. A blocking statement "blocks" trailing statements.
In a non-blocking statement, RHS will be evaluated at the beginning of the time step. Then the LHS will be updated at the end of the time step.
2. How do you model a synchronous and asynchronous reset in Verilog?
Answer
Synchronous reset:
always @(posedge clk)
begin
--
if(reset)
--
end
Asynchronous reset:
always @(posedge clk or posedge reset)
begin
--
if(reset)
--
end
The logic is very simple: In asynchronous reset, the always block will invoked at positive edge of the reset signal, irrespective of clock's value.
3. What happens if there is connecting wires width mismatch?
Answer
For example there are two signals rhs[7:0], and lhs[15:0]. If we do rhs = lhs. Then it is equivalent to rhs = lhs[7:0]. Assignment starts from LSBs of the signals, and ends at the MSB of smaller width signal.
4. What are different options that can be used with $display statement in Verilog?
Answer
%b or %B - Binary.
%c or %C - ASCII character.
%d or %D - Decimal.
%h or %H - Hexadecimal.
%m or %M - Hierarchical name.
%o or %O - Octal.
%s or %S - String.
%t or %T - Time.
%v or %V - Net signal strength.
5. Give the precedence order of the operators in Verilog.
Answer
You can find it here
6. Should we include all the inputs of a combinational circuit in the sensitivity list? Give reason.
Answer
Yes, in a combinational circuit all the inputs should be included in the sensitivity list other wise it will result in a synthesis error.
7. Give 10 commonly used Verilog keywords.
Answer
always, and, assign, begin, case, default, else, end, module, endmodule, reg, net, etc.
Click here for the complete list.
8. Is it possible to optimize a Verilog code such that we can achieve low power design?
Answer
9. How does the following code work?
wire [3:0] a;
always @(*)
begin
case (1'b1)
a[0]: $display("Its a[0]");
a[1]: $display("Its a[1]");
a[2]: $display("Its a[2]");
a[3]: $display("Its a[3]");
default: $display("Its default")
endcase
end
Answer
The case checks a[0] to a[3], if any one of the is 1'b1, then the first appearing 1'b1 will be executed. suppose a[0] = 0, a[1] = 1, a[2] = 1, and a[3] = 0,then Its a[1] will be displayed. If all are zeros then Its default, will be displayed.
10. Which is updated first: signal or variable?
Answer
Signal.
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