VHDL code For Tri State Buffer

What is Tri-State Buffer ?

A tri-state buffer has two inputs: a data input 'a' and a control input e. The control input acts like a valve. When the control input is active, the output is the input. That is, it behaves just like a normal buffer. The "valve" is open.

When the control input is not active, the output is "Z". The "valve" is open, and no electrical current flows through. Thus, even if 'a' is 0 or 1, that value does not flow through.

Block schematics:

courtesy: wikipedia   

Truth Table:

INPUT		OUTPUT
a	e	y
0	0	0
1		1
X	1	(high impedance)

Program:

--VHDL Code for tri state buffer--
--Declare library--
library ieee;
use ieee.std_logic_1164.all;
--Entity named tri_buff
entity tri_buff is
port(
--8 BIT bus input
a:in std_logic_vector(7 downto 0);
--8 BIT bus output
y:out std_logic_vector(7 downto 0);
--enable for buffer
e:in std_logic);
end tri_buff;

--Architecture for the tristate buffer
architecture dataflow of tri_buff is
--Signal declaration
signal h:std_logic_vector(7 downto 0):="ZZZZZZZZ";
begin
--Select 'e'
--assign output to input when e=0
--assign output to high impedence state otherwise 
with e select
y<=a when '0',
h when others;
end dataflow;

Output:

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