Verilog program for AND Gate using switch level programming

`timescale 1ns / 1ps
module AndGateUsingSwitchLevel(out,a,b);
input a,b;
output out;
wire d,c;
supply1 pwr;
supply0 gnd;
pmos p1(d,pwr,a);
pmos p2(d,pwr,b);
pmos p3(out,pwr,d);
nmos n1(d,c,a);
nmos n2(c,gnd,b);
nmos n3(out,gnd,d);
endmodule