Verilog code for UP/Down Counter using behavioral style of modeling

`timescale 1ns / 1ps

module UpDOwnCounterUsingBehavioural(clk,up,a);
input clk,up;
output[3:0]a;
reg [3:0]a=4'b0000;
always @(posedge clk)
if(up)
begin
a=a+4'b0001;
end
else
begin
a=a-4'b0001;
end
endmodule