Verilog code for SR-Latch Using NAND gates

`timescale 1ns / 1ps
module SRLatchUsingStructural(s,r,clk,q,qbar);
input s,r,clk;
output q,qbar;
wire a,b;
nand n1(q,a,qbar);
nand n2(qbar,b,q);
nand n3(a,s,clk);
nand n4(b,r,clk);
endmodule