Verilog code for mod-4 counter using D-Flipflop

`timescale 1ns / 1ps
module Mod4CounterUsingDFF(q,clk,rst);
input clk,rst;
output [1:0]q;
DFlipflopUsingBehavioural d1(q[0],~q[1],clk,rst);
DFlipflopUsingBehavioural d2(q[1],q[1]^q[0],clk,rst);
endmodule