verilog code for Master slave SR-Flipflop using structural style of modeling

`timescale 1ns/1ns
`resetall
module MasterSlaveSRFlipFlop(q,qbar,s,r,clk);
input s,r,clk;
output q,qbar;
wire l,m;
SRLatchUsingStructural s1(s,r,clk,l,m);
SRLatchUsingStructural s2(l,m,~clk,q,qbar);
endmodule