Verilog code for the Full Adder Using Behavioral style

`timescale 1ns / 1ps
module FullAdderUsingBehaviouralStyle(cout,sout,a0,a1,cin);
input a0,a1,cin;
output cout,sout;
reg cout,sout;
always @(a0,a1,cin)
case ({a1,a0,cin})
3'b000: begin sout=0;cout=0;end
3'b001: begin sout=1;cout=0;end
3'b010: begin sout=1;cout=0;end
3'b011: begin sout=0;cout=1;end
3'b100: begin sout=1;cout=0;end
3'b101: begin sout=0;cout=1;end
3'b110: begin sout=0;cout=1;end
3'b111: begin sout=1;cout=1;end
endcase
endmodule