Verilog code for Even Odd Counter using behavioral style of coding

module EvenOddCounterUsingBehavioural(q,clk,even);
input even,clk;
output [3:0]q;
reg [3:0]q=1'b0000;
always @(posedge clk)
begin
if(even && q%2!=0)
begin
q=q+1; //q=4'b0000;
end
else
if(even)
begin
q=q+2;
end
end
always@(posedge clk)
begin
if(~even && q%2==0)
begin
q=q+1;//q=4'b0001;
end
else
if(~even)
begin
q=q+2;
end
end

endmodule