Verilog code for D Flipflop using behavioral style of modeling

`timescale 1ns / 1ps
module DFlipflopUsingBehavioural(q,d,clk,rst);
input d,rst,clk;
output q;
reg q;
always @(posedge clk)
if (rst==1'b1)
q<=1'b0;
else
q<=d;
endmodule