Verilog Code for the 2:1 MUX Using gate level

`timescale 1ns / 1ps
module MuxUsingGateLevelCode(s,in,out);
input s;
input [1:0]in;
output out;
wire a,b,c;
//a,b,c are temporary variable for storing s' , in[0].s' , in[1].s respectively
not(a,s);
and(b,in[0],a);
and(c,in[1],s);
or(out,b,c);
endmodule