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Proving 1=2!!!! (fun maths)

on August 13, 2012

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8051 assembly code to generate triangular wave

ORG 0 CLR A UP:INC A MOV P2,A CJNE A,#0FFH,UP LCALL DELAY DOWN: DEC A MOV P2,A CJNE A,#00,DOWN LCALL DELAY SJMP UP END

8086 ASSEMBLY CODE TO CHECK PASSWORD AND VALIDATE USER

;;PASSWORD IS MASM1234 DATA SEGMENT PASSWORD DB 'MASM1234' LEN EQU ($-PASSWORD) MSG1 DB 10,13,'ENTER YOUR PASSWORD: $' MSG2 DB 10,13,'WELCOME TO ELECTRONICS WORLD!!$' MSG3 DB 10,13,'INCORRECT PASSWORD!$' NEW DB 10,13,'$' INST DB 10 DUP(0) DATA ENDS CODE SEGMENT ASSUME CS:CODE,DS:DATA START: MOV AX,DATA MOV DS,AX LEA DX,MSG1 MOV AH,09H INT 21H MOV SI,00 UP1: MOV AH,08H INT 21H CMP AL,0DH JE DOWN MOV [INST+SI],AL MOV DL,'*' MOV AH,02H INT 21H INC SI JMP UP1 DOWN: MOV BX,00 MOV CX,LEN CHECK: MOV AL,[INST+BX] MOV DL,[PASSWORD+BX] CMP AL,DL JNE FAIL INC BX LOOP CHECK LEA DX,MSG2 MOV AH,09H INT 21H JMP FINISH FAIL: LEA DX,MSG3 MOV AH,009H INT 21H FINISH: INT 3 CODE ENDS END START END

Verilog code for serial Adder

Block Diagram : `resetall `timescale 1ns/1ns //shift register to store the two inputs a and b to be added module shift(y,d,clk); input [3:0] d; input clk; output [3:0] y; reg [3:0] y; initial begin assign y=d; end always @(posedge clk) begin assign y=y>>1; end endmodule //serial in parallel out register to store the 4 bit sum module sipo(y,s,clk); input s; input clk; output [3:0] y; reg [3:0] y; always @(posedge clk) begin assign y={s,y[3:1]}; end endmodule //1 bit full adder module fa(s,cout,a,b,cin); input a,b,cin; output s,cout; assign {cout,s}=a+b+cin; endmodule //d flipflop to store the cout of each stage module dff(q,d,clk); input d,clk; output q; reg q; initial begin q=1'b0; end always @(posedge clk) begin q=d; end endmodule //main module serial adder// module serial(sum,cout,a,b,clk); input [3:0] a,b; input clk; wire [3:0] x,z; output [3:0] sum; output cout; wire s,cin; //input cin; //initial be...

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Proving 1=2!!!! (fun maths)

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