INTRODUCTION TO VHDL

VHDL(Very high speed integrated circuit Hardware Description Language ) is a hardware description language which describes the behavior of the circuit. This language is mainly used to implement digital logic.Almost all the Digital circuit can be implemented using this powerfull  tool.

VHDL is intended circuit for synthesis and simulation.All the constructs in VHDL are Simulatable but only some constructs are synthesizable.

Main application of VHDL is that it is used to program CPLD(Complex Programmable Logic Devic),FPGA(Field Programmable Gate Array) and also in the field of ASIC(Application Specific Integrated Circuit ).

The VHDL code is Concurrent (all the statements are executed parallel except the statements placed inside Process,Function or Procedure ).If you consider 'C' or Verilog,these are Sequential(Statements are executed one after the other,i.e Sequentially).

The Synthesis and simulation tools for VHDL are provided by EDA(Electronic Design Automation) companies lilke XILINX, ALTERA, MENTHOR GRAPIHCS etc .

While implementing a digital circuit first you write the Truth table,then you obtain the simplified logic expression for the circuit using K-Map or any other convenient method,draw the logic circuit for the expression and then write the VHDL code.

Example:

Half ADDER:

    step-1:

    Truth table of Halfadder:

a	b	S	C
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

   Step-2:

   K-Map of Half Adder:

  K-Map for Sum:

                                             

b\a	0	1
0	0	1
1	1	0

   K-Map for Carry:

                                                                        

b\a	0	1
0	0	0
1	0	1

 Step-3:

Simplified Logical Expression of Halfadder:

S=a XOR b

C=a AND b

Step-4:

Logic Circuit of Half adder:

Step-5:

VHDL CODE OF HALFADDER:

LIBRARY IEEE; --library declaration

ENTITY HALFADDER IS --ENTITY 

PORT(a,b:IN BIT; --input ports

     s,c:OUT BIT);--output ports

END FULLADDER; 

ARCHITECTURE dataflow OF HALFADDER IS --ARCHITECTURE

BEGIN 

s<=a XOR b;--SUM EXPRESSION

c<=a AND b;--CARRY EXPRESSION

END dataflow;

OUTPUT: