VHDL DATA TYPES

In general we may classify the VHDL data types in to two category, they are user defined data types and predefined data types.
Predefined data types:
We can find many predefined data types in VHDL. They are embedded in the Libraries/packages.
let us consider list of Packages and hence we discuss the Data types contained in those packages.

• STD package of Library STANDARD defines BIT, BOOLEAN, REAL and INTEGER data types.
• STD_LOGIC_1164 package of Library IEEE defines STD_LOGIC and STD_ULOGIC data types.
• STD_LOGIC_ARITH package of library IEEE defines SIGNED and UNSIGNED data types and also several data conversion functions like CONV_INTEGER(P), CONV_STD_LOGIC_VECTOR(P,Q), CONV_SIGNED(P,Q),CONV_UNSIGNED(P,Q).
• STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED  packages of Library IEEE used to treat STD_LOGIC_VECTOR data types as SIGNED and UNSIGNED data types respectively.

User Defined Data types:
VHDL allows user to describe his own data types,These data types are called as User defined data types.
Two categories of the User defined data type are Integer type and Enumerated data type .
User defined Integer data type: