Fundamental VHDL Units

VHDL is composed of three fundamental units.They are Library declaration,Entity and Architecture.


Library:
Library contains collection of commonly used pieces of VHDL code. Usually in Library, codes are written in the form of Function, Procedure and Packages(these are discussed later). Main part of VHDL code is Library declaration.
syntax of library declaration :
LIBRARY Library_name;                                     
USE Library_name.Package_name.Package_Parts;
Library_name:
Library name usually IEEE(Institute of Electronics and Electrical Engineers). Other Libraries are WORK,STD Library, but STD library is default library,hence it is  not needed to specify in code.
Package_name:
Package_name specifies the package of the library to be used in the code. For example in IEEE library commonly used packages are STD_LOGIC_1164, STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED etc.
Package_parts:
It specifies the parts of the package to be used in the code.                  


Example:
LIBRARY IEEE;                            
USE IEEE.STD_LOGIC_1164.ALL;




LIBRARY IEEE;                               
USE IEEE.STD_LOGIC_ARITH.ALL;


Entity:
Entity is the list of input and output ports.This list also tells the specification of ports.

Syntax of Entity:

ENTITY Entity_name IS                              

PORT(Port_name:Signal_Mode Signal_type;

          Port_name:Signal_Mode Signal_type;

          ....................................................);

END Entity_name;                                     

Entity_name:

Entity name is User defined . But it should be meaning full.There are few rules for Defining Entity_name.

• Entity Name Should start with Alphabet.
• Special characters are not allowed in Entity ('_' is allowed )
• Name should be meaning full.

Port_Name:
This is name of the port.


Signal_Mode:


Signal_Mode specifies the mode of signal. It can be IN, OUT, INOUT  or BUFFER.
IN--> Port accept only input.
OUT-->Port Gives Output.
INOUT-->If the input and output should be passed through same port this mode is used(this is use full in the case of memory designing).
BUFFER-->This temporarily Stores signal.


Signal_Type:


Signa _type can be BIT, BIT_VECTOR, STD_LOGIC, STD_LOGIC_VECTOR.(these are discussed later).


Example:
Consider AND gate, Let A and B be the two i/p ports and Y be the o/p port.Entity of this is given by


ENTITY  and_gate IS  
PORT(A,B:IN BIT;    
          Y:OUT BIT);   
END and_gate;          

Architecture:
Architecture is the description of how the circuit should  behaves.
It's syntax is given as

Syntax of Architecture:


ARCHITECTURE ARCHITECTURE_NAME OF ENTITY_NAME IS 
(DECLARATIVE PART)                                                                
BEGIN                                                                                         
(CODE)                                                                                        
END ARCHITECTURE_NAME;                                                     


ARCHITECTURE_NAME :
It is user defined name.This can be any meaningful name.


PARTS OF ARCHITECTURE:
Architecture contains two parts, one is Declarative part and other is Code . In Declarative part we declare the signals required for Circuit but it is optional. Code contains the description of the circuit.


EXAMPLE:

Let us consider above example of AND gate. Architecture is given as


ARCHITECTURE DATAFLOW OF AND_GATE IS
BEGIN                                                                
Y<=A AND B;                                                     
END DATAFLOW;                                              


CODE STRUCTURE:

I will explain this code structure by an Example of FULL ADDER .


Truth table of Full-Adder:

A	B	C	S	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

 K-MAP for Full-Adder:

K-map for SUM:

c\a b	00	01	11	10
0	0	1	0	1
1	1	0	1	0

 K-map for Carry:

c\a b	00	01	11	10
0	0	0	1	0
1	0	1	1	1

Simplified Expression for Full Adder:


S= A XOR B XOR C;

Cout = (A AND B)OR(B AND C)OR(C AND A);

Logic Circuit for Full Adder:

VHDL CODE FOR FULL ADDER:



LIBRARY IEEE;      --LIBRARY DECLARATION
USE IEEE.STD_LOGIC_1164.ALL;  -- LIBRARY DECLARATION
ENTITY FULL_ADDER IS -- ENTITY WITH ENTITY NAME FULLADDER
PORT(A,B,C:IN STD_LOGIC; --PORTS A,B,C WITH IN MODE AND OF TYPE STD_LOGIC
S,Cout:OUT STD_LOGIC);-- PORTS S,Cout OF TYPE STD_LOGIC
END FULL_ADDER; --END OF ENTITY


ARCHITECTURE DATAFLOW OF FULL_ADDER IS --ARCHITECTURE 
BEGIN
S<=A XOR B XOR C; --SUM EXPRESSION
Cout<=(A AND B)OR(B AND C)OR(C AND A); -- CARRY EXPRESSION
END DATAFLOW; --END OF ARCHITECTURE


OUTPUT:

VHDL TIPS:

• VHDL is case insensitive .
• dash (--) indicates comment lines.