Vhdl code to generate calender



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity date is
port(clk,reset:in std_logic;
date:out integer;
year:inout integer);
end date;
architecture arch of date is
type month is(jan,feb,mar,apr,may,jun,jul,aug,sep,oct,nov,dec);
signal pr_month,nx_month:month;
type day is(sun,tus,sat,mon,wed,thur,fri);
signal pr_day,nx_day:day;
signal temp:integer;
signal count:integer range 1 to 31;
signal yeartemp:integer range 2000 to 3000:=1991;
signal shifttemp:integer range 1 to 31:=2;
signal junk:integer range 0 to 1:=1;
begin
process(clk)
begin
if reset='1' then
pr_day<=tus;
pr_month<=jan;
date<=1;
elsif rising_edge(clk) then
shifttemp<=shifttemp+1;
count<=count+1;
pr_day<=nx_day;
date<=count;
if(shifttemp=temp+junk)then
count<=1;
junk<=0;
shifttemp<=1;
end if;
end if;
if(shifttemp=1 and rising_edge(clk))then
pr_month<=nx_month;
end if;
end process;
process(pr_day)
begin
case pr_day is
when sun=>
nx_day<=mon;
when mon=>
nx_day<=tus;
when tus=>
nx_day<=wed;
when wed=>
nx_day<=thur;
when thur=>
nx_day<=fri;
when fri=>
nx_day<=sat;
when sat=>
nx_day<=sun;
when others=>null;
end case;
end process;
process(pr_month)
begin
case pr_month is
when jan=>temp<=31;
nx_month<=feb;
when feb=>if(year mod 4 = 0)then
temp<=29;
else
temp<=28;
end if;
nx_month<=mar;
when mar=>temp<=31;
nx_month<=apr;
when apr=>temp<=30;
nx_month<=may;
when may=>temp<=31;
nx_month<=jun;
when jun=>temp<=30;
nx_month<=jul;
when jul=>temp<=31;
nx_month<=aug;
when aug=>temp<=31;
nx_month<=sep;
when sep=>temp<=30;
nx_month<=oct;
when oct=>temp<=31;
nx_month<=nov;
when nov=>temp<=30;
nx_month<=dec;
when dec=>temp<=31;
nx_month<=jan;
yeartemp<=yeartemp+1;
when others=>null;
end case;
end process;
year<=yeartemp;
end arch;







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