VHDL Code for timer

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Here is a VHDL code for a timer which consisting of a STOP START RESET Signal, when you give start signal as ‘1’ the timer starts counting and when you give stop signal as ‘1’ count will stop and the timer will remain in the same state irrespective of clock. The capacity of clock is max 9min:59sec when it crosses this limit it resets to 00min:00sec and when reset is ‘1’ the timer will reset  to 00min:00sec irrespective of clock ,start ,stop  signal. By using same logic you can design digital clock. I hope this program is use full for you. If any doubt you can mail to hariprasadmdg@gmail.com J J

Code:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clock IS
port(reset,clk,start,stop:in std_logic;
min,sec:out integer);
end clock;
architecture behaviour of clock is
begin
process(reset,clk,start,stop)
variable tempmin,tempsec:integer:=0;
begin
if(reset='1')then
tempmin:=0;
tempsec:=0;
elsif(stop='1')then
min<=tempmin;
sec<=tempsec;
elsif(start='1')then
if(rising_edge(clk))then
tempsec:=tempsec+1;
if(tempsec=60)then
tempsec:=0;
tempmin:=tempmin+1;
if(tempmin=10)then
tempmin:=0;
end if;
end if;
end if;
end if;
min<=tempmin;
sec<=tempsec;
end process;
end behaviour;

Output:


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