VHDL code for jk flipflop using case

library ieee;
use ieee.std_logic_1164.all;
entity jk_ff is
port(j,k,rst,clk:in std_logic;
q,qbar:out std_logic);
end jk_ff;
architecture behavioural of jk_ff is
signal input:std_logic_vector(1 downto 0);
begin
input<=j&k;
process(clk,j,k,rst)
variable set:std_logic:='0';
begin
if(rst='0')then
if rising_edge(clk) then
case input is
when "10"=>
set:='1';
when "01"=>
set:='0';
when "11"=>
set:=not set;
when others=>
null;
end case;
end if;
else
set:='0';
end if;
q<=set;
qbar<=not set;
end process;
end behavioural;