VHDL code for full subtractor

code--

library ieee;
use ieee.std_logic_1164.all;
entity fullsub is
port(a,b,c:in std_logic;
s,cout:out std_logic);
end fullsub;
architecture dataflow of fullsub is
begin
s<=a xor b xor c;
cout<=(not a and (b or c)) or (b and c);
end dataflow;