vhdl code for conversion of fractional binary to real

NOTE: go to edit there u click on preference n change the preference to unsigned decimal before you running the program :) :)

code: 


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity frctn_real is
port(a:in std_logic_vector(3 downto 0);
y:out real);
end frctn_real;
architecture arch of frctn_real is
begin
process(a)
variable t,r:real;
begin
t:=0.0;
for i in 0 to 3 loop
if (a(i)='1')then
t:=t+(1.0/2.0**(i+1));
end if;
end loop;
y<=t;
end process;
end arch;