vhdl code for 4 bit synchronous counter using jk flipflop

code for jk ff--


library ieee;
use ieee.std_logic_1164.all;
entity jk_ff is
port(j,k,rst,clk:in std_logic;
q,qbar:out std_logic);
end jk_ff;
architecture behavioural of jk_ff is
signal input:std_logic_vector(1 downto 0);
begin
input<=j&k;
process(clk,j,k,rst)
variable set:std_logic:='0';
begin
if(rst='0')then
if rising_edge(clk) then
case input is
when "10"=>
set:='1';
when "01"=>
set:='0';
when "11"=>
set:=not set;
when others=>
null;
end case;
end if;
else
set:='0';
end if;
q<=set;
qbar<=not set;
end process;
end behavioural;


code for counter --

library ieee;
use ieee.std_logic_1164.all;
entity synchcnt is
port(rst,clk:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end synchcnt;
architecture behavioural of synchcnt is 
component jk_ff is
port(j,k,rst,clk:in std_logic;
q,qbar:out std_logic);
end component;
signal i,j,k:std_logic;
begin
i<=q(0);
j<=q(0) and q(1);
k<=q(0) and q(1) and q(2);
a1:jk_ff port map('1','1',rst,clk,q(0),qbar(0));
a2:jk_ff port map(i,i,rst,clk,q(1),qbar(1));
a3:jk_ff port map(j,j,rst,clk,q(2),qbar(2));
a4:jk_ff port map(k,k,rst,clk,q(3),qbar(3));
end behavioural;